There were 2 parts to the simulation. The first was an interesting job: to guarantee that the design satisfied the timing needs of the DDR3 by considering time and length suit. The 2nd part was to guarantee signal stability; factors to consider for impedance matching would make certain no impedance gaps would trigger signal honesty concerns. While the signal rates were high, they were low enough for loss to be a considerable worry, given the trace sizes involved.
Among the DDR3 needs was that the address and control data would certainly exist in a fly-by setting, linking in between the controller and all 4 memory ICs. To comply with the timing constraint that needed the clock course to be longer compared to the data and DQS lines, one needed to include length to the clock. This, naturally, contravened office requirements. Along with this, for the very first and 2nd memory IC, earlier along the path, the information in some cases came from a part of the FPGA, that made the data course rather long.
The trace size in between the memories and FPGA varied between 1.5″ to a number of inches in length. The address and control signals took a trip to all four memory components, while the data were coming from a part of the FPGA that was potentially farther away. It was an obstacle to maintain delays to ensure that the write timing in the DDR3 would certainly function.
To make certain timings matched, standard routing was carried out first then matched the lengths. It was decided which layers would be utilized for each and every of the signals and teams travelled together; for example, each information lane was placed on the very same layer. An effort was made to minimize the number of vias and other features needed to reach the end course.
The FPGA had some versatility with respect to which pins could be used for which objectives. Nonetheless, as rate boosted, it postured constraints due to the fact that particular groups of pins for specific lanes of data were required. The largest trouble came with the address and control lanes, all traveling in large teams on the same layers of the PCB board.
The challenge came when it was time to match sectors. This was challenging because of the lack of area. A basic point-to-point suit for the address and control lanes wouldn’t be enough. Rather, we matched every section: between the controller and the initial IC, first IC to the 2nd IC, and so forth. Luckily, since the ICs were a certain range apart, it was basically a point-to-point match, and the trace sizes were comparable. The biggest obstacle was matching the section from the FPGA to the first memory IC. The lengthiest course defined the length of time the trace needed to be, and sometimes we should boost the trace by a large fraction of an inch to suit this. To include so much length, trombones or accordions were required, which took up space on the board.
The BGA bundles for the HDMI and FPGA controller postured trace breakout concerns. In a similar way, the HDMI controller was a very fine-pitch BGA; it really did not have very many pins, yet it was a 0.5 mm pitch BGA, so breaking out in a traditional pattern would be hard. Although the FPGA wasn’t a particularly huge or thick component, because of the board’s small size, traces might just burst out on the east and west sides instead of the typical north-south-east-west pattern.