The EA Video game company engaged VR Systems to produce a prototype of screen connected to the headgear. This headgear display screen offered a heads-up screen of instrumentation and digital depictions of crucial information. The safety helmet was the heart of the Virtual Reality equipments, enabling the customers to benefit from the whole system for remarkable gaming experience.
PCB requirements. The safety helmet screen supported the rigid flex PCB in its mechanical housing, and an HDMI cord fed into the video clip resource. An optical cord connected to the screen, which carried light to the headset’s LCOS microdisplay. The light illuminated the display and was predicted into waveguides that provided info to the customer’s eyes.
The headset display screen was one of the first reported binocular HMDs in growth utilizing a liquid crystal and silicon microdisplay. This innovative dramatically decreased the price, quantity and weight of standard helmet-mounted displays, replacing cumbersome optics systems with light-weight, slim, translucent diffractive optics. The screen’s physical needs positioned fascinating challenges for the rigid flex PCB.
1. The system had to be little enough to install to the pilot’s helmet and enable activity without causing discomfort.
2. To avoid user injury, it needed to instantly launch all links to the plane in the event the pilot needed to eject from the aircraft.
3. The boards should be flexible enough to twist around the system’s optical components and fit ports at different angles.
4. As a result of size restraints, the design can just break out traces on the eastern and western sides of the main FPGA element, instead of a north-south-east-west pattern.
Xilinx provided valuable info regarding time of trip inside the bundle, as did the IBIS models of the Micro memory modules. The bundle for the memory component was substantially smaller than the Xilinx FPGA, and the Xilinx time of trip info was important. We had the ability to modify out the differences in the memory components after layout was completed.
The design made use of a Xilinx FPGA and a 64-bit wide DDR3 memory bus, where each of 4 parts had a 16-bit vast information bus. Timing was matching to a few picoseconds on the trip times through the board. One of the more tough parts of the design was that the link in between the FPGA and memory called for simulation at a really broadband, so the timing restraints were tight. With such tight margins, it was essential to think about the travel time of flight inside the plans along with on the board. For these factors, die-to-die time of trip was picked, in contrast to simply pin-to-pin time of trip.