DC/DC converter PCB design, Part 3

One crucial innovation in the field of DC/DC power converters is the awareness of higher and greater thickness layouts. In the promote smaller-footprint solutions, designers are currently concentrating on usable power density to extract one of the most power each unit area or quantity from the converter circuit. Because the power converter is a vital as well as ubiquitous piece of the total remedy, a thoughtful printed circuit board (PCB) layout represents a chance to boost density while supplying added system-level advantages, also. One instance is electro-magnetic disturbance (EMI), which is a significantly troublesome concern during item design as well as qualification. A compact, maximized power phase design enhances EMI in terms of both exhausts as well as immunity.

In this three-part series [1], I reviewed PCB format factors to consider for fast-switching DC/DC converters utilizing a step-by-step technique. Actions 1 and also 2 from part 1 examined the PCB layer stackup as well as determined the high-di/dt existing loops and high-dv/dt voltage nodes of the converter. Actions 3 and 4 partly 2 supplied an evaluation of power phase as well as control IC element positioning for ideal switching in addition to thermal and also EMI efficiency. In this last installment, I cover steps 5 and 6: the transmitting of essential traces for eviction drives, current sense and comments network; and also an evaluation of power and also ground (GND) aircraft design of the multilayer PCB substratum as well as ground splitting up methods. For a total recap of DC/DC converter PCB format standards, see Table 1.

Step 5: Route the MOSFET gateway drives, current sense, comments and various other critical traces

Comprehending gate-loop and also common-source parasitic inductances

MOSFET switching actions and also the effects for waveform buzzing, changing loss, device tension and also EMI are very closely related to the parasitic inductances of the changing loop and also gate circuit emerging from tool package and also PCB format connections [2,3] From Figure 1, we need to recognize the duty of two parasitical inductances emerging from the entrance drive circuit design.

Figure 1: SyncFET parasitic turn-on causes undesirable shoot-through in phase-leg configurations. This is related to variation present from switch-node voltage dv/dt (a), and also negatively induced source voltage from body diode reverse-recovery-current di/dt (b).

LG is the self-inductance of the gate loop, including lumped contributions from the MOSFET package deal and also PCB trace routing, and LS is the common-source or mutual inductance shared by the drain and also gateway present paths [4,5] As received Figure 1, common-source inductance LS1 of the control MOSFET (CtrlFET) increases switching loss since the di/dt of the main loophole creates an adverse comments voltage that restrains the surge as well as fall times of the gate-source voltage. Throughout body diode reverse recovery, common-source inductance LS2 adds to spurious turn-on of the simultaneous MOSFET (SyncFET).

Lessening gate-circuit parasitic inductances

Formerly I went over the top- and bottom-layer layouts for the 4-switch buck-boost converter [5] in components 1 and also 2. Numbers 2, 3 reveal the inner-layer art work for this PCB.

Eviction driver traces running from the control IC to the 4 MOSFETs, which lie on layers 3 and 4, are kept as brief and also direct as possible to minimize gateway inductance. A Kelvin connection links eviction drive return traces directly to their particular MOSFET resource terminals, lessening common-source inductance. The return currents for the low-side MOSFET gateway drives flow on the GND aircraft back to the PGND pin of the IC. To decrease gateway loop location, gateway and resource traces are routed side-by-side as differential pairs utilizing 20-mil trace sizes.

Gate loophole parasitic inductance also enhances the moment needed to refresh the boot capacitor. This is particularly crucial for high responsibility cycle operating problems when the SyncFET has a short transmission time. Number 1 highlights the boot capacitor refresh present course in green.

Routing present and voltage sense traces

Figure 3a shows the traces for present feeling routed as a snugly combined differential set from the shunt resistor to the IC current sense inputs. Kelvin sensing at the shunt is essential for precision. Keepout limits make sure that vias related to the sense return trace are isolated from GND aircrafts, and also existing sense filter parts are located as close as feasible to the IC.

Figure 3b reveals the VOUT sense area at the point where the most precise policy is accomplished, generally on the cheapest layer in the stackup before current flows to the tons. VIN and also VOUT feeling traces are low resistance to GND, yet are still vulnerable to the high di/dt loops of the converter.

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