DC/DC converter PCB design, Part 2

High efficiency, high density and also reduced production expenses drive the constant development of DC/DC converters for an increasingly large variety of power supply applications for automobile, commercial, personal electronic devices and communications markets. To attain these design targets, a small yet innovative published motherboard (PCB) format design of the switching converter goes a long means in the push for a smaller impact option. The PCB design itself is generally a multi-objective discipline, as it straight affects electrical, mechanical, thermal and also electromagnetic actions.

Component 1 of this three-part collection [1] focused on power converter PCB design and relevant considerations. The four-switch buck-boost converter topology provides a convenient system to study PCB design, as you can quickly theorize the analysis to various other geographies. Actions 1 and 2 (covered in component 1) talked about multilayer PCB stackup and also the important current loopholes as well as voltage nodes of the switching converter. Right here in part 2, I will certainly check out action 3, the power element positioning for optimum switching regulatory authority efficiency, looking also at power phase thermal design and also electro-magnetic interference (EMI) considerations. Step 4 explores steering IC as well as small-signal part floor preparation and location.

Action 3: Power-stage element positioning

Based on the high di/dt existing loop recognition outlined in action 2 (part 1), thoughtful and also tactical positioning of the power stage parts is vital. With raising switching rates and lower package parasitics, the bottleneck in power MOSFET changing efficiency is shifting from silicon to the commutating loop parasitic resistance [2] Utilizing the synchronous buck-boost geography example layout in recommendation 3, the display capture in Figure 1 highlights positioning of power MOSFETs, large element ratio footprint existing shunt, and also input as well as result ceramic capacitors on the PCB’s top layer.

Figure 1: To the left is the PCB leading layer with power-stage component design showing tight Air Conditioner current-loop conduction paths. To the right is a schematic of the 4-switch buck-boost power train, consisting of power MOSFETs, shunt, inductor, and input as well as output capacitors.

The lower-profile MOSFETs (3 mm x 3 mm) and ceramic capacitors (1210 footprint) are intentionally found on the top side of the PCB. The taller parts (inductor and mass capacitors) are on the lower side. Input capacitors are located near buck-leg MOSFETs. Outcome capacitors are situated adjacent to boost-leg tools, resulting in a limited, symmetrical format for both changing legs. Note that the shunt resistor increases the size of the location of both switching loopholes. A shunt resistor with a wide aspect proportion (1225 footprint) and also a shorter conduction course gives reduced inductance as well as decreased lengths of power loopholes 1 as well as 2, signified by the while borders in Figure 1.

H-field self-cancellation

Power-loop parasitic inductance increases MOSFET changing loss and also peak drain-to-source voltage spikes. It likewise aggravates switch-node voltage buzzing, affecting broadband EMI in the 50- to 300-MHz array. While lessening the physical dimension of the loop by focusing on component positioning is important to reduce loop inductance, noise combining additionally depends on field distribution/orientation, making the design of a PCB’s internal layers notable.

As reviewed in recommendations 4– 8, an easy shield layer is developed by putting a ground plane as close as feasible to the changing loophole using a minimal dielectric thickness. The straight existing flow on the top layer sets up a vertical flux pattern. The resulting electromagnetic field induces a current, contrary in direction to the power loophole, in the shield layer. By Lenz’s regulation, the present in the guard layer creates a magnetic area to counteract the initial power loop’s magnetic field. The outcome is an H-field self-cancellation that amounts to lower parasitical inductance, lowered switch-node voltage overshoot, and also boosted suppression of EMI [7] Having an uninterrupted, continual shield plane on layer 2 underneath and at closest distance to the power loop provides the most effective efficiency. Slim intralayer spacing is specified in the PCB stackup, making use of a 6-mil core dielectric for instance.

Power stage thermal design

While a high-density format is usually positive for conversion performance as transmission voltage drops are lowered, it might create a thermal efficiency bottleneck. A push-pull dynamic remains in play here: The same power dissipation in a smaller sized impact ends up being unacceptable. To take full advantage of thermal efficiency in convective airflow, place the MOSFETs on the top of the PCB. In this arrangement air movement is not watched by taller parts such as the inductor as well as electrolytic capacitors. Depending upon the application, it is possible to find the inductor on the bottom side of the PCB, because it may hinder warm transfer if positioned on the top. Owing to its size, the inductor fundamentally serves as its own warmth sink.

With respect to the 4-switch buck-boost converter being talked about here, the low-side MOSFET of the non-switching leg is held back in pure dollar or boost methods. This offsets the surrounding high-side gadget that carries out the inductor existing constantly with concomitant power loss. On the other hand, with deep buck or boost operation (that is, low dollar or high increase responsibility cycle), the switching-leg MOSFET option tilts towards managing low-side power loss and also temperature increase. As revealed inFigure 1, the high-side MOSFETs’ drains pipes are connected with short links to the VIN or VOUTpower terminals via heat-spreading copper aircrafts. Their drain tabs are additionally joined by countless thermal vias to equivalent copper airplanes under layer. Thus, the high-side MOSFETs are effectively heat-sinked.

The thermal challenge of this design is the low-side MOSFETs whose drain tabs are attached to switch-node copper polygons with via connections to the inductor listed below. Currently, the essential variable below is switch-node copper location. Provisioning for low EMI positions a focus on a marginal switch-node copper area to reduce capacitive coupling related to high dv/dt switch-node voltage changes [8] and reduce e-field radiated exhausts. Nevertheless, a bigger switch-node copper location helps in thermal dispersing relevant to dissipation from the inductor and low-side MOSFETs. A PCB format for bigger 5-mm x 6-mm footprint MOSFETs with lower thermal insusceptibility is achieved with a relatively minor edit to the layout in Figure 1.

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